The present disclosure relates to methods for fabricating semiconductor devices, and, more particularly, to methods for forming gates in gate-last processes, and to gate areas formed by the methods.
As integrated circuit (IC) size decreases, control of the distribution in the height of a gate also may decrease. In particular, as embedded source/drain technologies and elevated source/drain technologies are introduced to form a source/drain of a gate-last process, control of a gate height may be difficult.
A gate-last process is a process in which a gate is formed last. The gate-last process may include chemical mechanical polishing (CMP) of an interlayer dielectric (ILD), etching or CMP of a gate mask, removal of a dummy gate, and an aluminum Damascene process.
However, a reduction in the height of a gate may result from the gate-last process. For example, as a result of decreased IC design size, a gate height may be relatively low. On the other hand, the height of a gate may be designed to exceed the height of an elevated source/drain. Accordingly, the gate may have a height that is designed to be in a relatively narrow range.
FIGS. 1(a), 1(b), and 1(c) are side views of a cross-section of a gate area formed in a gate-last process. FIG. 1(a) illustrates a gate area that is planarized by CMP of an ILD. FIG. 1(b) illustrates a gate area in which a gate mask is etched. FIG. 1(c) illustrates a gate area in which a gate mask is CMP-ed. FIG. 2 is a scanning electron microscope (SEM) image showing a side view of a gate area formed by over-etching in a gate-last process.
Referring to FIGS. 1(a), 1(b), 1(c), and 2, a gate area in a gate-last process may include a semiconductor substrate 10, a dummy gate 20, a gate mask 30, a spacer 40, and an interlayer dielectric (ILD) 50. As illustrated in FIG. 1(a), an ILD 50 CMP process may be performed until the gate mask 30 is exposed. In doing so, the amount of the gate mask 30 that remains after the ILD 50 CMP process may vary according to the density of a pattern of the dummy gate 20. For example, more of the gate mask 30 may remain at a portion where the density of the pattern of the dummy gate 20 is high. As a result, the gate height may have a wide distribution.
Also, the gate mask 30 removal process (removal by etching) of FIG. 1(b) may be burdensome to subsequent processes because a local dent may be generated in an upper portion of the spacer 40 as a result of over-etching. Referring to FIG. 1(c)'s gate mask 30 removal process (removal by CMP), if the polishing continues into the dummy gate 20, then the reduction in the gate height may be significant.
If the distribution in the height of a gate is too wide, then the resulting problems may include a resistance defect, source/drain exposure after dummy gate 20 exposure, contamination due to electrode material exposure, or a dummy gate 20 removal defect.